1. Field of the Invention
The present invention relates to integrated circuit memories generally, and, in particular, to integrated circuit memories with write tracking.
2. Description of the Related Art
Memory devices generally employ a write tracking scheme to track events in a write operation of data to memory. In a conventional tracking scheme, an internal clock is generated with an external clock. The generated internal clock, in turn, generates a self-timed word-line (STWL) that enables multiple bitcells in a self-timed column, imitating a load of an actual bitline. The STWL triggers the multiple bitcells in the self timed column through digital programming that controls the discharge rate of the self-timed bitline to ensure enough differential signal drive on the actual bitlines for a successful read operation. A sense amplifier enable signal (SEN) is then generated after ensuring sufficient differential signal at statically worst-case sense-amplifier internal nodes. Sufficient SEN pulse width is required to complete the sensing and digitization of the signal. When the SEN closes, the complete read cycle is then closed by pre-charging sense amplifier internal nodes and bitlines. However, since no real tracking of the write into the memory array occurs, this conventional tracking scheme mainly tracks the read operation accurately, instead of the write operation.
Other existing write tracking schemes track the write operation through triggering the write into a dummy array that requires a PRESET operation (i.e., setting the memory cell contents to predefined values in every tracking cycle) followed by a dummy write to detect a “Low” to “High” transition. Due to the additional PRESET operation, however, the write cycle time increases significantly, limiting the overall cycle time.